NXP Semiconductors /MIMXRT1011 /LPSPI1 /CR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MEN_0)MEN 0 (RST_0)RST 0 (DOZEN_0)DOZEN 0 (DBGEN_0)DBGEN 0 (RTF_0)RTF 0 (RRF_0)RRF

MEN=MEN_0, RRF=RRF_0, DBGEN=DBGEN_0, RTF=RTF_0, DOZEN=DOZEN_0, RST=RST_0

Description

Control Register

Fields

MEN

Module Enable

0 (MEN_0): Module is disabled

1 (MEN_1): Module is enabled

RST

Software Reset

0 (RST_0): Module is not reset

1 (RST_1): Module is reset

DOZEN

Doze Mode Enable

0 (DOZEN_0): LPSPI module is enabled in Doze mode

1 (DOZEN_1): LPSPI module is disabled in Doze mode

DBGEN

Debug Enable

0 (DBGEN_0): LPSPI module is disabled in debug mode

1 (DBGEN_1): LPSPI module is enabled in debug mode

RTF

Reset Transmit FIFO

0 (RTF_0): No effect

1 (RTF_1): Transmit FIFO is reset

RRF

Reset Receive FIFO

0 (RRF_0): No effect

1 (RRF_1): Receive FIFO is reset

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